The present invention relates to a method for forming a copper line of a semiconductor device, and more particularly, to a method for forming a copper line having a self-assembled monolayer for use in ULSI semiconductor devices in which the method is less prone to creating unwanted voids and seams in the resultant copper line.
As integrated circuits become more highly resolved, i.e., higher integration, due to demands for higher performances and then physical limitations necessarily arise when adopting the existing materials and processes to make these highly integrated circuits.
For example, aluminum is currently chosen as a material for forming a metal line which electrically connects elements in an integrated circuit. Aluminum exhibits excellent electrical conductivity and is corrosion resistant. Aluminum can also be easily etched in a dry type environment technique. Furthermore aluminum is highly adhesive to SiO2 which is often used as a dielectric. Unfortunately, as line widths of these highly integrated semiconductor devices decrease down to the nanometer level, aluminum exhibits a number of undesirable properties for these purposes. In particular, the resistance of the aluminum ULSI metal lines increases. As a result, problems arise which are related to time delays, noise generation and power consumption. Furthermore, as the width of line decrease down to the ULSI level, the EM (electro migration) and the SIM (stress-induced migration) characteristics and the reliability of semiconductor device is expected to be compromised if aluminum is used.
Copper is most actively being researched as an alternative to aluminum primarily because copper has a specific resistance of 1.7 uΩcm which is lower than 2.65 uΩcm of aluminum. Further, it is known that copper is about two times more superior than aluminum in terms of their respective EM characteristics and the SIM characteristics.
Copper is not easy to etch. Because of this fact, damascene processes are often times used to form copper lines. In a method for forming a copper line by using a damascene process, after first defining a metal line forming region, a copper layer is deposited to fill in the metal line forming region. Then, the copper layer is polished down usually using CMP (chemical mechanical polishing) process to eventually define the copper metal line.
When filling in the copper layer in the metal line forming region, electroplating is often employed. A conductive layer is needed to enable electroplating and is generally formed using a PVD (physical vapor deposition) process. In this regard, as the width of a trench decreases, the aspect ratio of the trench necessarily increases. Then when the conductive layer is formed using a PVD process, step coverage is prone to being degraded largely because of a shadow effect. As a consequence, when filling in the metal line forming region with copper, voids are likely to be created in the metal line forming region. Under this situation, electroless plating has been proposed as an alternative to the electroplating.
Electroless plating has been widely used in printed circuit boards since 1960. In electroless plating, a metal layer is formed through self-oxidation and reduction without supplying electrons from an outside source.
In order to apply electroless plating at a ULSI (ultra-large-scale integrated) circuit scale, i.e., below a sub-micrometer level, it is necessary to uniformly form a copper seed layer to a thickness of several nanometers on the surface of the metal line forming region. However, in the case of a conventional sensitizing-activation method, due to the fact that catalytic particles have a wide size distribution that ranges from several nanometers to several micrometers, then it is understandable that unwanted agglomeration of these catalytic particles can occur. As a result of using these catalytic particles that have wide size distributions then voids and seams are likely to be created when plating copper with electroless plating techniques. As a result the reliability of a copper line at the ULSI scale become a problem because of the size distribution of these catalytic particles.